The present invention relates to an improved semiconductor wafer surface and a method of treating a semiconductor wafer surface having exposed copper regions or copper alloy regions in a cleaning process for cleaning the semiconductor wafer surface, and more particularly to a method of forming a semiconductor device using the surface-treated semiconductor wafer.
In recent years, as a material of metal interconnections in the semiconductor device, copper or copper alloys containing copper at not less than 80% has often been used. Such interconnections made of copper or copper alloys will hereinafter referred to as Cu-interconnections. The Cu-interconnections are formed by the damascene method in the interconnection grooves in the semiconductor substrate. FIGS. 1A through 1C are fragmentary cross sectional elevation views illustrative of the damascene method for forming the interconnection in the interconnection groove in the semiconductor substrate.
With reference to FIG. 1A, an insulation film 12 such as SiO2 film is formed over a semiconductor substrate 10. An interconnection groove is selectively formed in the insulation film 12, wherein the bottom of the interconnection groove comprises a part of the top surface of the semiconductor substrate 10. Namely, a part of the top surface of the semiconductor substrate 10 is shown in the interconnection groove. A barrier metal layer 14 such as Ta or TaN is formed on the top surface of the insulation film 12 as well as on the side walls and the bottom of the interconnection grooves, whereby the barrier metal layer 14 is in contact with the part of the top surface of the semiconductor substrate 10. A Cu-seed layer 15 is further deposited on the barrier metal layer 14 by a sputtering method or a chemical vapor deposition method. A Cu-layer 16 is formed on the Cu-seed layer 15 by an electroplating method, so that the Cu-layer 16 completely fills the interconnection groove and extends over the insulation film 12.
With reference to FIG. 1B, a semiconductor wafer 1 is loaded to a cleaning apparatus, so that a chemical mechanical polishing method is carried out to selectively remove the barrier metal layer 14, the Cu-seed layer 15 and the Cu-layer 16, so that the barrier metal layer 14, the Cu-seed layer 15 and the Cu-layer 16 remain only within the interconnection groove, whereby a Cu-interconnection 17 is formed in the interconnection groove.
A scrub cleaning process is carried out for removing particle contaminations from the above planarized surface of the semiconductor wafer 1. Subsequently, a spin cleaning process is carried out for removing metal contaminations from the above planarized surface of the semiconductor wafer 1 by use of a carboxylic based cleaning solution, such as an oxalic acid solution. Further, a spin-rinse dry process is carried out for rinsing the cleaning solution and subsequently drying the surface of the semiconductor wafer 1. The semiconductor wafer is then unloaded from the cleaning apparatus.
With reference to FIG. 1C, the semiconductor wafer 1 is loaded into a growth chamber, so that an Si3N4 film 18 serving as a copper-diffusion stopper insulating film is formed over the cleaned and planarized surface of the semiconductor wafer 1. An SiO2 inter-layer insulator 19 is formed on the Si3N4 film 18.
In accordance with the above conventional processes, the semiconductor wafer 1 is exposed to an air or an atmosphere after the semiconductor wafer 1 is unloaded from the cleaning apparatus and before the semiconductor wafer 1 is loaded into the growth chamber. A time duration between after the semiconductor wafer 1 is unloaded from the cleaning apparatus and before the semiconductor wafer 1 is loaded into the growth chamber depends upon a waiting time for loading the semiconductor wafer into the growth chamber. The waiting time may be, actually, for example, one day or more.
The above conventional method raises the following problem. If the copper diffusion stopper insulating film is formed on the semiconductor wafer having already exposed to the atmosphere, then an adhesion between the Cu-surface and the copper diffusion stopper insulating film is deteriorated.
Further, during the process for forming the copper diffusion stopper insulating film or the later process thereto, application of a stress is applied to the film or a heat treatment may generate a hillock on the Cu-surface.
If the deterioration in the adhesion between the Cu-surface and the copper diffusion stopper insulating film appears, then a current stress due to a current through the Cu-interconnection causes copper atoms to enter into a gap between the Cu-surface and the copper diffusion stopper insulating film, whereby a short circuit is formed between adjacent two of the Cu-interconnections. As a result, the reliability of the semiconductor device is deteriorated. Further, the above generation of the hillock also deteriorates the reliability of the semiconductor device.
In the above circumstances, it had been required to develop a novel semiconductor wafer surface and a method of treating the semiconductor wafer surface free from the above problem.